1. Field of the Invention
The present invention relates generally to timing circuits used in computer systems, and, more particularly, to a circuit and method to program the starting phase of the spread spectrum of a clock output.
2. Background Information
Semiconductor devices have increased in speed and degree of integration, leading to problems related to EMI (electromagnetic interference) due to electromagnetic wave radiation from associated devices. As the operation frequency has increased, the wavelengths have become shorter and the wiring length of a connecting circuit has become almost as short as the wavelength of a high frequency signal. Therefore, the connecting sections of wires may serve as antennas and electromagnetic wave radiation is increased. The electromagnetic wave radiation of electronic devices using semiconductor devices which operate at a high clock frequency causes adverse effects, such as malfunctions due to mutual interference between electronic device and interference with communication devices. In digital systems, clocks can be the noisiest sources of EMI radiation. They are generally the highest frequency sources in the system and drive the heavy capacitive load with fast edge rates. The problems related to EMI are reduced by improving the arrangement of circuits, providing adequate shielding, and on the like. However, portable equipment is required to be more compact and lighter every year, and shielding mechanisms have often proved difficult to implement. In conventional methods, the operating clock frequency of a semiconductor device is changed slightly and/or the peak of noise is scattered by the addition of a jitter to a clock signal. In one example of a conventional method, spread spectrum clock generation (SSCG) is utilized. Spread spectrum circuits operate by ‘spreading’ the frequency of a clock signal over a narrow band of frequencies to reduce the peak EMI energy. In a conventional spread spectrum solution, when a counter value changes, overshoots occurs at the beginning of the first pulse of the resulting waveform and undershoots occur at the bottom of the first pulse. The overshoot and undershoot typically start oscillating outside the desired spread range of the system.
FIG. 1 illustrates a block diagram of a conventional SSCG circuit designated by a general reference character 100. The SSCG circuit 100 generates a clock output CK (102) from a reference clock signal CLK (101). The frequency of the clock CK 102 output is M/N times that of the reference clock signal CLK (101), by utilizing a PLL (Phase Locked Loop) circuit as a divider. The SSCG circuit comprises a 1/N divider 111, a frequency phase comparator 112, a charge pump (CP) 113, a loop filter 114, a voltage control oscillator (VCO) 117, a 1/M divider 118, a modulator 115, and a voltage addition circuit 116.
Referring to FIG. 1, the frequency phase comparator 112 detects a phase difference between the CLK 101 divided by a factor of N and the CK 102 divided by a factor of M, and outputs a signal to control the CP 113 in accordance with the phase difference. The CP 113 outputs a signal to charge and discharge the loop filter 114 in accordance with the phase difference, and a differential voltage in accordance with the phase difference is generated at one end of the loop filter 114. In a conventional clock generation circuit, which does not carry out the spread spectrum modulation, a differential voltage is applied to the VCO 117 and a clock with a constant period is generated accordingly. In the SSCG circuit 100, however, the modulator 115 outputs a spectrum modulation signal, which has a small amplitude and changes in a predetermined spread spectrum modulation period.
FIG. 2 shows the spectrum modulation signal characterized by the general designation 200. Referring again to FIG. 1, the spectrum modulation signal, such as that illustrated in FIG. 1, can be added to the differential voltage in the voltage addition circuit 116 and applied to the VCO 117. The amplitude of the spectrum modulation signal is sufficiently smaller than that of the differential signal, and the spread spectrum modulation period is sufficiently longer than a period of the generated clock CK 102. As a result, the period of the generated clock CK 102 changes in a predetermined cycle, with the period M/N times the period of the reference clock signal CLK 101 being the center. The change of period and the cycle are determined by the spectrum modulation signal generated by the modulator. The response time of the PLL circuit is set to a time sufficiently shorter than the period of the spectrum modulation signal. The PLL will track the spectrum modulation signal.
Conventional SSSG methods have the disadvantage of a fixed starting phase of the spread profile with a resulting increase in emission energy (EMI) of the spread profile when a plurality of clocks start at the same phase of the profile. It would therefore be desirable to have an improved spread spectrum of a clock output that has a lower EMI of the spread energy with a plurality of clocks that start their spread in a predetermined delta phase to each other.